This invention relates to a semiconductor integrated circuit device including a memory device having a super self-refresh mode.
Basically, this invention relates to a memory device (for example, a DRAM of a clock synchronization type known as a SDRAM (synchronous dynamic random access memory) using a DRAM (dynamic random access memory) cell and relates to control of a refresh operation of reading charge information of the DRAM cell and rewriting the same before charges of the DRAM cell fade away and are lost. In particular, this invention relates to a super self-refresh operation which has a longer cycle as compared with a normal self-refresh operation.
United States Patent Application Publication No. 2002/0018389 A1 discloses a SDRAM having a super self-refresh mode. In order to achieve the super self-refresh mode, an example of the SDRAM disclosed in FIG. 1 of the above-mentioned publication comprises first through fourth ECC (error correcting code)-CODEC (coder-decoder) circuits as first through fourth coder/decoder circuits in one-to-one correspondence to first through fourth banks of the SDRAM and a control logic (i.e., a control circuit) connected to the first through the fourth ECC-CODEC circuits. In order to achieve the super self-refresh mode, another example of the SDRAM disclosed in FIG. 2 of the above-mentioned publication comprises a single ECC-CODEC circuit in common to first through fourth banks of the SDRAM and a control logic (i.e., a control circuit) connected to the ECC-CODEC circuit.
Furthermore, the above-mentioned publication discloses that, when a DRAM enters an operation mode in which only a data holding operation is performed, a check bit for error detection/correction for a plurality of data is generated and stored by using the ECC-CODEC circuit. Refresh operation is performed in a refresh cycle which is lengthened within an allowable range of error occurrence by an error correcting operation using the check bit (the refresh operation of such a long cycle is a super self-refresh operation). Before the DRAM returns from the data holding operation to a normal operation, an error bit is corrected by using the above-mentioned data and the check bit (paragraphs [0011] and [0012]).
However, the above-mentioned publication does not disclose a circuit structure of an ECC controller connected between the control logic of the SDRAM and the first through the fourth ECC-CODEC circuits or between the control logic of the SDRAM and the single common ECC-CODEC circuit to control the ECC-CODEC circuits or circuit under control of the control logic of the SDRAM.
It is therefore an object of this invention to provide a semiconductor integrated circuit device comprising an ECC controller for controlling an ECC-CODEC circuit under control of a control logic of an SDRAM.
Other objects of this invention will become clear as the description proceeds.